The present invention relates to image processing apparatus which store taken image data into a memory and effect image processing on the stored image data.
In general, those constructed as shown in FIG. 1A are known as the image processing apparatus for effecting image processing on taken image data. In FIG. 1A, numeral 101 denotes an imaging device such as CCD. An image data acquired by the imaging device 101 is subjected, as preprocessing, to such simple processing as a simple WB processing, OB subtraction and knee processing at a preprocessing section 102. Subsequently, after subjected to the main image processing such as YC image generation and resizing at an image processing section 103, it is outputted for example onto a TFT monitor through a display section 104. Denoted by numeral 105 is the CPU for controlling each section.
In thus constructed image processing apparatus, the clock rate for the imaging data generated at the imaging device 101, the processing operation clock rate at the image processing section 103, and the display operation clock rate at the display section 104 are usually different from each other. Accordingly, in the case for example of the image processing apparatus of the above construction where imaging data taken by the imaging device is directly and continuously processed to be displayed, a time lag from the taking of image to its displaying can be reduced because processing is directly effected. In this case, however, an extremely large line memory is usually required to accomplish an image processing with effecting a spatial filter processing, resulting in the problem of an increased circuit size.
By contrast, one for example disclosed in Japanese Patent Application Laid-Open 2000-236460 is known as having construction as shown in FIG. 1B where DRAM 106 is provided so that image data taken at the imaging device 101 and processed at preprocessing section 102 is once stored into DRAM 106, and the image data is then read out from DRAM 106 and transmitted to the image processing section 103 or display section 104 for an image processing or displaying.
In such a case where DRAM 106 is provided to once store the image data, adjustment of the timings of starting the processing of the image processing section 103 and display section 104 is effected by CPU 105. If the timing adjustment is to be effected frame by frame, processing is effected according to the procedure shownin FIG. 2A. In particular, taking of image data into DRAM 106 is started through the preprocessing section 102, and, when the taking of image data of one frame has been complete, the preprocessing section 102 notifies CPU 105 by an interrupt of the completion of the taking into DRAM 106. When CPU 105 is interrupted to confirm the completion of the taking of image data into DRAM 106, the processing at the image processing section 103 is started. When the image processing by the image processing section 103 has been complete, then, CPU is similarly notified by an interrupt of the completion of the image processing so that the display section 104 reads and displays the data after the image processing.
If such control technique for effecting image processing after causing DRAM 106 to store the image data corresponding to one frame is used, an extremely large line memory becomes unnecessary and load on CPU 105 is reduced. There is a problem however that time lag from the image taking to its displaying becomes greater.
To solve such problem, in a recently used technique, the image processing units of image data are divided as shown in FIG. 2B and timing adjustment is effected by the divided image processing units.
Particularly, in the procedure according to this control technique of the image processing, when the taking of image data into DRAM 106 is started through the preprocessing section 102, CPU 105 at first places the stored amount of image data under surveillance. When CPU 105 confirms that some lines of image data necessary for image processing have been stored, it starts the image processing section 103 to effect image processing. Upon completion of the processing of the predetermined image data at the image processing section 103, CPU 105 is notified of the completion of the processing by an interrupt. When CPU 105 receives the interrupt notification, CPU 105 checks again the image data amount that the preprocessing section 102 has stored into DRAM 106. After detecting that data necessary for the next image processing has been stored into DRAM 106, the image processing section 103 is started again to start the processing. Thereafter such processing procedure is repeated to process one frame.
By effecting such divided image processing, the divisionally processed image data can be transmitted to a display section without waiting for the completion of the image processing corresponding to one frame. Accordingly, it becomes possible to start display operation during the image processing of the one frame. It is thereby possible to effect image processing without requiring an extremely large line memory and at the same time with reducing time lag from the start of image taking to the displaying.